The demand for smaller-sized, high-speed, high-density multi-chip packages (MCP) is growing by the day . Stacking Silicon to increase packing density in IC’s is not a new concept, but recently stacking has gained a new level of importance as the process is being introduced to make microprocessors and is slated to come into the mainstream by 2008,Currently chip components are connected by wire bonding, requiring vertical spacing between dies that is tens of microns deep and horizontal spacing on the package board hundreds of microns wide for the die-connecting wires.Stacked silicon, rather than placed side-by-side shortens on chip data travel distances, ultimately saving a whole lot of space on chip and offering an opportunity to drive Moore’s law forward .

“Through-silicon vias” (TSV) is the technology employed for stacking ,which uses vertical connections etched through the silicon wafer and filled with metal. This concept has been described by other chip manufacturers before . Intel revealed thier plans for TSV at the spring IDF 2005 and most recently Samsung announced that it has developed the first all-DRAM stacked memory package using TSV technology, which will soon result in memory packages that are faster, smaller and consume less power, Samsung’s technology forms laser-cut micron-sized holes that penetrate the silicon vertically to connect the memory circuits directly with a copper filling, eliminating the need for gaps of extra space and wires protruding beyond the sides of the dies.
While TSV is still in its early stages, the technology represents the next step in innovative packaging solutions which have become increasingly important to enable high-speed, high-density and high- performance Semiconductor solutions .



Ever since AMD announced its AM2 socket processors last year, the industry has gradually shifted away from DDR towards DDR2 , DDR2 memory doubles the bus frequency at the same clock rate as DDR which effectively doubles the data rate , or simply put a DDR2 module is faster than DDR module .Nvidia is using the free space on SPD ROM chip on memory to store different performance profiles ( SPD stands for serial presence detect which is a chip inside the memory module which tells the PC what size and type and make it is and also holds some other information) , I guess these memory modules will replace the current generation of SLI ready memory , most probably it would hold different overclocking profiles which can be easily altered using a front-end application.
Intel recently announced that the next generation of chips on their core micro-architecture will support DDR3 memory , but for that we ll probably have to wait till Q3 2007 .So folks this is the time to start saving up for that upgrade to a monster R600 card from ATI and some super fast DDR3 memory .